Switched capacitor, charge redistribution successive approximation routine (SAR) analog to digital converters (ADCs) are commonplace. Such converters provide good resolution in combination with the ability to asynchronously sample an input signal and to output their answers without incurring a pipeline delay overhead. Presently, such converters can accept differential inputs and accurately convert those inputs into digital form provided the common mode component of the input is fixed at a value required by the converter. This is typically accomplished through external circuitry such as an operational amplifier or instrumentation amplifier circuit which can translate the input common mode component to the value required by the converter for accurate operation. However these circuits can introduce noise or gain error, and consume power and space, and are best avoided if possible.
A prior art differential input, charge redistribution 6-bit (for simplicity only) SAR ADC is shown in FIG. 1. It samples a pair of input voltages, VinP and VinN, with respect to a bias voltage, Vbias, and, under the control of a SAR controller, produces a sequence of binary decisions at the output, OUT, which correspond to the digital equivalent of the input voltage difference with respect to the reference voltage difference, (VrefP−VrefN).
The SAR ADC system 100 shown comprises two digital-to-analog converters (DACs), DACP and DACN, a comparator 12, and an SAR controller/engine 40 to drive the DACs. Each DAC comprises (for this example) a 6-bit binary-weighted capacitor array 14P, 14N, where the total capacitance of each individual array 14P, 14N is C. The DACs further comprise two corresponding sets of switches 16P, 16N to connect the respective DAC inputs to VinP/N, and corresponding sets of switches 18P, 18N to connect the respective DAC inputs to VrefP/N (as appropriate), as well as switches 20P, 20N to connect the DAC outputs, TopP, TopN, to the bias voltage point, Vbias, which is an arbitrary but constant voltage typically mid-way between the comparator's input range or the power supply voltages VDD and GND.
In the example shown in FIG. 1, each of the weighted capacitor arrays 14N (associated with DACN) and 14P (associated with DACP) includes capacitors C1, C2, C3, C4, C5, C6 and terminating capacitor C7. The capacitances of such capacitors, with respect to the total capacitance C of the array, is as follows: C1=C/2, C2=C/4, C3=C/8, C4=C/16, C5=C/32, C6=C/64 and C7=C6=C/64. The sum of the capacitances of C1 to C7 equals C. In real world implementations of this circuit, additional detrimental parasitic capacitors will exist, and these have, for convenience, been shown as extending from the common rail TopP to ground and from the common rail TopN to ground and have been designated Cpp and Cpn respectively.
Each of switch sets 16N (associated with DACN) and 16P (associated with DACP) includes switches Si1, Si2, Si3, Si4, Si5, Si6 and Si7. Each of switch sets 18N (associated with DACN) and 18P (associated with DACP) includes switches S1, S2, S3, S4, S5, S6 and S7.
The DAC outputs TopP and TopN provide input voltages to the comparator 12. The plates of the capacitors directly connected to the outputs TopP and TopN are referred to as the “top plates” with the other capacitor plates referred to as the “bottom plates.” The switches to Vbias are referred to as the “top-plate switches” 20P and 20N.
During operation, an input voltage is sampled as charge across the input capacitors with the DAC bottom plates connected to the input voltages VinP and VinN through switches in the switch sets 16P and 16N. When the top-plate switches 20P and 20N are closed, the DAC is said to be “sampling the input”, and at the instant at which the top plate switches open, the DAC is said to have “taken the sample”.
After sampling the input voltage, the ADC 100 carries out an iterative process, referred to as a successive approximation routine (SAR). Using the P-side of the circuit as an example, the SAR iterative process begins by connecting in turn the bottom plate of each of the capacitor array 14P capacitors C1 . . . C7, through its corresponding switch Si1 . . . Si7 in switch bank 16P and a corresponding switch S1 . . . S7 in switch bank 18P, to either the positive reference voltage VrefP or the negative reference voltage VrefN. Each capacitor, e.g. C4, represents one of the bits in the digital output word of the ADC 100, the most significant (MSB) of which corresponds to capacitor C1 and the least significant bit (LSB) of which corresponds to capacitor C6.
In an exemplary embodiment, a bit has a binary value of 1 when the bottom plate of the associated capacitor, e.g. C1, is connected to the positive reference voltage Vrefp and the bit has a binary value of 0 when the bottom plate of the capacitor, e.g. C4, is connected to the negative reference voltage VrefN through switch bank 18. In this example, switch Si4 would get switched to connect capacitor C4 to the Vref voltages (i.e. not the VinP position) and switch S4 would get aligned to connect capacitor C4 to either VrefP or VrefN, depending on whether C4 was to represent a logical 1 or 0, respectively.
As those skilled in the art will appreciate the SAR controller will step through such a series of SAR iterations, starting with the MSB capacitor and ending with the LSB capacitor. During each iteration, each capacitor is switched to either VrefP or VrefN such that the top plate voltages, TopP and TopN, converge with each iteration. When the iterations have completed, the last-used digital word (the value of the bits to which the capacitors were connected) is selected as the output of the ADC.
FIGS. 2A-C show an aspect of the differential operation of the ADC 100 of FIG. 1. FIGS. 2A-C, and all subsequent similar figures, depict the top plate voltages TopP and TopN as a function of time. During the time interval depicted, the bottom plate voltages are initially connected to their respective VinP and VinN inputs in the sampling phase. During this time the top plate voltages settle towards Vbias due to the closure of the sampling switches 20P and 20N. Next the sampling switches are opened, thus sampling the inputs, and the bottom plates are switched to the SAR controller and a succession of digital words are presented to the DACs during the conversion process. The SAR words presented to the SARP and SARN switches for bit trial #1 are SARP=1000000 and SARN=0111111 where the bus contents from left to right represent assignments from the MSB capacitor (C1) to the LSB capacitor (C6) and finally the terminating capacitor (C7). The progression of the SAR words from bit trial #1 to bit trial #6 with each successive approximation is a function of the analog input sampled.
In FIGS. 2A-C, and all subsequent similar figures, the positive reference voltage, VrefP, is 5V, and the negative reference voltage, VrefN, is 0V, with the corresponding restriction that each input is valid only between 0V and 5V. The Full Scale Range (FSR) of the converter is the difference between the maximum differential input, Vdiff_max, and the minimum differential input, Vdiff_min, according to:Vref=VrefP−VrefN=5−0=5VVdiff_max=VinP_max−VinN_min=Vref−0=5VVdiff_min=VinP_min−VinN_max=0−Vref=−5VFSR=Vdiff_max−Vdiff_min=Vref−−Vref=10V
In each of these figures the Vbias voltage is 2.5V and the applied differential input voltage is 0.3*FSR, or 3V. As this patent relates to the ability to accommodate varying common mode voltages, the set of three graphs within each figure vary only by the common mode voltage associated with the differential input voltage. This differential input voltage corresponds to an ideal ADC conversion result, from MSB to LSB, of “001100” on SARP and “110011 . . . ” on SARN. The differential relationship between the top plates at each bit trial, i.e. is TopP>TopN, is shown above the top plate waveforms as either a 1 or 0. This 1 or 0 will also be the output provided by the comparator at the end of each bit trial. If the comparator output is 1, i.e. TopP is greater than TopN, then TopP is decreased by subtracting the bit weight under trial from SARP and TopN is increased by adding the bit weight under trial to SARN (also known as discarding the bit weight under trial). If the comparator output is 0, i.e. TopP is less than TopN, then the bit weight under trial in both SARP and SARN is left unaltered (also known as keeping the bit weight under trial). The next bit trial then begins by asserting the bit weight being trialled in SARP and de-asserting the bit weight being trialled in SARN. Those skilled in the art will appreciate the consequential convergence of the top plate voltages and also the fact that the SARP and SARN busses are related to each other—in this case they are complements of each other. Thus, in this example the 6 bit output from the comparator was 110011, and the conversion result is the inverse of this, namely 001100.
FIG. 2A shows the progress of the conversion with the input common mode voltage, Vcm, set to 2.5V. It is important to appreciate that when the sample was taken both top plate voltages were essentially equal to Vbias, and that upon the completion of the conversion both top plates had returned to that same voltage. The previously mentioned parasitic capacitors, Cpp and Cpn, therefore remain unchanged in their voltage. This represents a “return-to-zero” condition whereby any top plate parasitic capacitances, either linear or non-linear, which would otherwise corrupt the conversion process, are essentially in the same state as they were during sampling and, thus, have been prevented from contributing errors.
FIG. 2B similarly shows the progress of the conversion but with the input common mode voltage, Vcm, increased from 2.5V to 3V. The SAR controller, which only monitors the difference between the top plates, will act identically to FIG. 2A. However one skilled in the art will immediately appreciate that the top plates no longer ‘return to zero’ (i.e. Vbias) and that the deleterious top plate parasitic capacitors have been charged to a value which is a function of the different common mode voltage, Vcm. This charge was ‘stolen’ from the sampled input charge and the SAR algorithm, unaware of this missing charge, is likely to yield errors if the effect is large enough or if the accuracy called for is high enough.
FIG. 2C similarly shows the progress of the conversion but with the input common mode voltage decreased to 1.5V, yielding correspondingly similar errors as with FIG. 2B.
It can be thus seen that allowing the input common mode voltage, Vcm, to vary will limit the accuracy of the converter. However, real world input signals frequently have variable common mode voltages. While it is possible to circumvent this through external circuitry, it is desirable to have the converter perform this function without the need for such circuitry.